Polarity Control at Runtime:from Circuit Concept to Device Fabrication

Semiconductor device research for digital circuit design is currently facing increasing challenges to enhance miniaturization and performance. A huge economic push and the interest in novel applications are stimulating the development of new pathways to overcome physical limitations affecting conventional CMOS technology. Here, we propose a novel Schottky barrier device concept based on electrostatic polarity control. Specifically, this device can behave as p- or n-type by simply changing an electric input bias. This device combines More-than-Moore and Beyond CMOS elements to create an efficient technology with a viable path to Very Large Scale Integration (VLSI). This thesis proposes a device/circuit/architecture co-optimization methodology, where aspects of device technology to logic circuit and system design are considered. At device level, a full CMOS compatible fabrication process is presented. In particular, devices are demonstrated using vertically stacked, top-down fabricated silicon nanowires with gate-all-around electrode geometry. Source and drain contacts are implemented using nickel silicide to provide quasi-symmetric conduction of either electrons or holes, depending on the mode of operation. Electrical measurements confirm excellent performance, showing Ion/Ioff > 10^7 and subthreshold slopes approaching the thermal limit, SS ~ 60mV/dec (~ 63mV/dec) for n(p)-type operation in the same physical device. Moreover, the shown devices behave as p-type for a polarization bias (polarity gate voltage, Vpg) of 0V, and n-type for a Vpg = 1V, confirming their compatibility with multi-level static logic circuit design. At logic gate level, two- and four-transistor logic gates are fabricated and tested. In particular, the first fully functional, two-transistor XOR logic gate is demonstrated through electrical characterization, confirming that polarity control can enable more compact logic gate design with respect to conventional CMOS. Furthermore, we show for the first time fabricated four- transistors logic gates that can be reconfigured as NAND or XOR only depending on their external connectivity. In this case, logic gates with full swing output range are experimentally demonstrated. Finally, single device and mixed-mode TCAD simulation results show that lower Vth and more optimized polarization ranges can be expected in scaled devices implementing strain or high-k technologies. At circuit and system level, a full semi-custom logic circuit design tool flow was defined and configured. Using this flow, novel logic libraries based on standard cells or regular gate fabrics were compared with standard CMOS. In this respect, results were shown in comparison to CMOS, including a 40% normalized area-delay product reduction for the analyzed standard cell libraries, and improvements of over 2× in terms of normalized delay for regular Controlled Polarity (CP)-based cells in the context of Structured ASICs. These results, in turn, confirm the interest in further developing and optimizing CP devices, as promising candidates for future digital circuit technology

On the Query Strategies for Efficient Online Active Distillation

Deep Learning (DL) requires lots of time and data, resulting in high computational demands. Recently, researchers employ Active Learning (AL) and online distillation to enhance training efficiency and real-time model adaptation. This paper evaluates a set of query strategies to achieve the best training results. It focuses on Human Pose Estimation (HPE) applications, assessing the impact of selected frames during training using two approaches: a classical offline method and a online evaluation through a continual learning approach employing knowledge distillation, on a popular state-of-the-art HPE dataset. The paper demonstrates the possibility of enabling training at the edge lightweight models, adapting them effectively to new contexts in real-time

Mass Segregation in NGC 2298: limits on the presence of an Intermediate Mass Black Hole

[abridged] Theoretical investigations have suggested the presence of Intermediate Mass Black Holes (IMBHs, with masses in the 100-10000 Msun range) in the cores of some Globular Clusters (GCs). In this paper we present the first application of a new technique to determine the presence or absence of a central IMBH in globular clusters that have reached energy equipartition via two-body relaxation. The method is based on the measurement of the radial profile for the average mass of stars in the system, using the fact that a quenching of mass segregation is expected when an IMBH is present. Here we measure the radial profile of mass segregation using main-sequence stars for the globular cluster NGC 2298 from resolved source photometry based on HST-ACS data. The observations are compared to expectations from direct N-body simulations of the dynamics of star clusters with and without an IMBH. The mass segregation profile for NGC 2298 is quantitatively matched to that inferred from simulations without a central massive object over all the radial range probed by the observations, that is from the center to about two half-mass radii. Profiles from simulations containing an IMBH more massive than ~ 300-500 Msun (depending on the assumed total mass of NGC 2298) are instead inconsistent with the data at about 3 sigma confidence, irrespective of the IMF and binary fraction chosen for these runs. While providing a null result in the quest of detecting a central black hole in globular clusters, the data-model comparison carried out here demonstrates the feasibility of the method which can also be applied to other globular clusters with resolved photometry in their cores.Comment: 21 pages, 3 figures, ApJ accepte

Regular Fabric Design with Ambipolar CNTFETs for FPGA and Structured ASIC Applications

In this paper, we propose for the first time the application of ambipolar CNTFETs with in-field controllable polarities to design regular fabrics with static logic. We exploit the high expressive power provided by complementary static logic built with ambipolar CNTFETs to design compact and efficient configurable gates. After evaluating a polarity-aware logic design for the configurable gates, we selected a number of gates with an And-Or-Inverter structure and produced a first comparison with existent medium-grained logic blocks, like the Actel ACT1 and 4-input LUTs [1]. Preliminary evaluation of our gates indicates improvements of around 47% over the ACT1 and of about 18× with respect to 4-input LUTs in terms of area×normalized delay

Mensurando a Maturidade da Cultura de Segurança no Trabalho: uma revisão das ferramentas existentes.

A culture of safety understood and practiced by all becomes an important factor for the prevention of accidents and occupational diseases. To measure the maturity of the security culture and verify the stage in which it is in an organization are used tools, also called factors. The present study sought to identify the tools used to measure the safety culture at work. In order to meet this objective, a bibliographical research was carried out on "tools to measure the maturity of the security culture", in the CAPES journal. This search resulted in 22 articles All relevant information on existing tools for measuring safety culture maturity was extracted, summarized and presented in this study. As results, it was found that among all the articles researched, five factors were most used to measure the safety culture in the organization.Una cultura de seguridad entendida y practicada por todos se convierte en un factor importante para la prevención de accidentes y enfermedades laborales. Para medir la madurez de la cultura de seguridad y verificar la etapa en que se encuentra en una organización se utilizan herramientas, también llamadas factores. El presente estudio buscó identificar las herramientas utilizadas para medir la cultura de seguridad en el trabajo. Para atender este objetivo se realizó una investigación bibliográfica sobre "herramientas para medir la madurez de la cultura de seguridad", en el portal del periódico CAPES. Esta búsqueda resultó en 22 artículos. Todas las informaciones relevantes, sobre las herramientas existentes para medir la madurez de la cultura de seguridad, fueron extraídas, resumidas y presentadas en este estudio. Como resultados se constató que, entre todos los artículos, se destacaron cinco factores más utilizados para medir la cultura de seguridad en la organización.Uma Cultura de segurança entendida e praticada por todos se torna um fator importante para prevenção de acidentes e doenças ocupacionais. Para mensurar a maturidade da cultura de segurança e verificar o estágio em que a mesma se encontra em uma organização são utilizadas ferramentas, também chamadas de fatores. O presente estudo buscou identificar as ferramentas utilizadas para mensurar a cultura de segurança no trabalho. Para atender este objetivo realizou-se uma pesquisa bibliográfica sobre “ferramentas para mensurar a maturidade da cultura de segurança”, no portal de periódico CAPES. Esta busca resultou em 22 artigos. Todas as informações relevantes, sobre as ferramentas existentes para mensurar a maturidade da cultura de segurança foram extraídas, sumarizadas e apresentadas neste estudo. Como resultados constatou-se que, dentre todos os artigos pesquisados, destacou-se cinco fatores mais utilizados para mensurar a cultura de segurança na organização

Alternative Design Methodologies for the Next Generation Logic Switch (invited paper)

Next generation logic switch devices are ex- pected to rely on radically new technologies mainly due to the increasing difficulties and limitations of state-of-the-art CMOS switches, which, in turn, will also require innovative design methodologies that are distinctly different from those used for CMOS technologies. In this paper, three alternative emerging technologies are showcased in terms of their re- quirements for design implementation and in terms of poten- tial advantages. First, a CMOS evolutionary approach based on vertically-stacked gate-all-around Si nanowire FETs is discussed. Next, an alternative design methodology based on ambipolar carbon nanotube FETs is presented. Finally, a novel approach based on the recently discovered memristive devices is presented, offering the possibility of combining memory and logic functions

Hyperspectral and LiDAR data for the prediction via machine learning of tree species, volume and biomass: a possible contribution for updating forest management plans

This work intends to lay the foundations for identifying the prevailing forest types and the delineation of forest units within private forest inventories in the Autonomous Province of Trento (PAT), using currently available remote sensing solutions. In particular, data from LiDAR and hyperspectral surveys of 2014 made available by PAT were acquired and processed. Such studies are very important in the context of forest management scenarios. The method includes defining tree species ground-truth by outlining single tree crowns with polygons and labeling them. Successively two supervised machine learning classifiers, K-Nearest Neighborhood and Support Vector Machine (SVM) were used. The results show that, by setting specific hyperparameters, the SVM methodology gave the best results in classification of tree species. Biomass was estimated using canopy parameters and the Jucker equation for the above ground biomass (AGB) and that of Scrinzi for the tariff volume. Predicted values were compared with 11 field plots of fixed radius where volume and biomass were field-estimated in 2017. Results show significant coefficients of correlation: 0.94 for stem volume and 0.90 for total aboveground tree biomass

A Schottky-Barrier Silicon FinFET with 6.0 mV/dec Subthreshold Slope over 5 Decades of Current

In this paper, we demonstrate a steep Subthreshold Slope (SS) silicon FinFET with Schottky-barrier source/drain. The device shows a minimal SS of 3.4 mV/dec and an average SS of 6.0 mV/dec over 5 decades of current swing. Ultra-low leakage floor of 0.06 pA/μm is also achieved with high Ion/Ioff ratio of 107